This invention relates generally to computer and microcomputer systems structure, particularly to a circuit technique for managing the computer system memory.
It is a common goal in any computer system, particularly in a microcomputer system, to minimize the amount of random access memory (RAM) that is required since memory elements are an expensive part of any system. At the same time, it is a goal of any computer structure to provide flexibility in programming so that the limitations on memory size do not create added problems for the programmer. As a result, a technique has been employed of using a separate memory management unit (MNU) disposed between the microprocessor or other central processing unit (CPU) and the RAM. Use of the MMU allows the program to call for data in the memory at "logical" addresses that are converted by it to "physical" memory addresses where the data actually resides. The physical memory actually allocated is generally much less than the logical memory assumed to be available by the program. Thus, the MMU is an important element in efficiently using the physical memory available to carry out the software operations commanded of the system.
As a particular example of such a system, the Z8001 microprocessor available from Zilog, Inc. is utilized with one or more Zilog Z8010 MMU memory management units. This particular microprocessor designates on a segment bus one of 128 different logical memory segments in which a particular location within the segment is designated on an address bus. Each of the 128 segments may have up to 64 K bytes of memory. The MMU may be utilized to control the size of each segment of the memory in increments of 256 bytes. The MMU contains a register for each of 64 memory segments that designates for the physical memory the actual beginning address of each physical segment as well as the size of that segment. The MMU's ability to control that size is useful for stack or variable size data memories. A variable stack memory size, for example, would occupy one of the 128 logical memory segments, resulting in eliminating usable logical memory within that segment that is outside the size of the stack.
It is a primary object of the present invention to provide an improved memory management system that better utilizes the available logical and physical memory space.